1. Field of the Invention
The present invention relates to a wiring substrate and a method for fabricating the wiring substrate, and more particularly to a wiring substrate for use in a semiconductor apparatus such as a BGA, and a method for fabricating the wiring substrate.
2. Description of the Background Art
In recent years, an electronic apparatus not only has its size and thickness reduced but also has its performance enhanced and its function diversified. In order to realize specifications of the electronic apparatus, a semiconductor apparatus, which is the most important component for the electronic apparatus, tends to have its size and thickness reduced, and further include the increased number of terminals. Under these situations, as a configuration of the semiconductor apparatus, a so-called BGA (Ball Grid Array) package, LGA (Land Grid Array) package, and the like are generally known. The BGA package and the LGA package include no external lead projecting from an outer circumference of a sealing resin portion although a conventional QFP (Quad Flat Package) includes the external lead. In these packages, solder balls are provided, as external electrodes for performing electrical connection, on the bottom surface of the semiconductor apparatus, so as to form a matrix.
A typical wiring substrate for use in a semiconductor apparatus will be described. FIG. 11 is a diagram illustrating a printed-wiring board 101 which is a typical wiring substrate for use in a semiconductor apparatus. FIG. 11(a) is a top view of the printed-wiring board 101. In FIG. 11(a), the printed-wiring board 101 is patterned with a conductor layer 102, and the conductor layer 102 is electrically connected through vias 103 to a conductor layer which is provided on the bottom surface of the printed-wiring board 101. On a bonding pad positioning area 105 of the printed-wiring board 101, a bonding pad 106 is provided so as to connect to the conductor layer 102, and a surface portion of each of the bonding pad 106 and the conductor layer 102 is Ni/Au-plated. A solder resist 104 is applied to portions other than the bonding pad positioning area 105 of the printed-wiring board 101.
FIG. 11(b) is a cross-sectional view of the printed-wiring board 101 shown in FIG. 11 (a) along lines A-B, and FIG. 12 is an enlarged view of a portion C shown in FIG. 11 (b). With reference to FIG. 11(b) and FIG. 12, a cross-sectional configuration of the printed-wiring board 101 will be described in detail. The conductor layer 102 with which the printed-wiring board 101 is patterned is laminated to both the top surface and the bottom surface of a substrate core 107. Further, the substrate core 107 has holes penetrating therethrough so as to form the vias 103. The surfaces of the vias 103 penetrating through the substrate core 107 are each copper-foil-plated, and therefore the conductor layers 102 provided on both the top and the bottom surfaces of the substrate core 107 are electrically connected to each other. The solder resist 104 is applied to portions other than the bonding pad positioning area 105 on the top surface of the printed-wiring board 101 and a ball positioning area 110 provided on the bottom surface of the printed-wiring board 101. The ball positioning area 110 is an area for allowing the printed-wiring board 101 to connect to an external electrode through a solder ball. Further, the vias 103 in which the substrate core 107 has the copper-foil-plated surface are filled with the solder resist 104. On the other hand, the bonding pad 106 is positioned in the bonding pad positioning area 105 which is open, and further the surface of the bonding pad 106 is Ni (108)/Au (109)-plated. Moreover, the surface of the conductor layer 102 in the ball positioning area 110 is Ni (108)/Au (109)-plated.
Next, a method for fabricating a typical wiring substrate for use in a semiconductor apparatus will be described. FIG. 13 is a diagram illustrating a method for fabricating the printed-wiring board 101 shown in FIG. 11. FIGS. 13 (a) to 13(g) are diagrams illustrating cross sections of the printed-wiring board 101 in fabrication process steps (a) to (g), respectively.
In a process step (a), the conductor layer 102 is laminated to the entire top and bottom surfaces of the substrate core 107. In a process step (b), the substrate core 107 having both the top and the bottom surfaces to which the conductor layer 102 is laminated is penetrated at a predetermined portion (for example, six portions in FIG. 13) by means of a drill or a laser, so as to form the vias 103. In a process step (c), the surface of each of the vias 103 penetrating through the substrate core 107 is copper-foil-plated. In a process step (d), a portion of the conductor layer 102 laminated to both the top and the bottom surfaces of the substrate core 107 is etched and removed, so as to form a wiring pattern. In a process step (e), the solder resist 104 is applied to both the top and the bottom surfaces of the substrate core 107 to which the conductor layer 102 is laminated so as to pattern the substrate core 107. Further, the vias 103 in which the substrate core 107 has the copper-foil-plated surface are filled with the solder resist 104. In a process step (f), the solder resist 104 is etched and removed in the bonding pad positioning area 105 on the top surface of the printed-wiring board 101 and the ball positioning area 110 on the bottom surface of the printed-wiring board 101. In a process step (g), the bonding pad 106 is positioned on the surface of the conductor layer 102 exposed in the bonding pad positioning area 105, and the bonding pad 106 is Ni (108)/Au (109)-plated. Further, the surface of the conductor layer 102 exposed in the ball positioning area 110 is Ni (108)/Au (109)-plated.
Next, an exemplary semiconductor apparatus using the printed-wiring board 101 shown in FIG. 11 and FIG. 13 will be described. FIG. 14 is a diagram illustrating a semiconductor apparatus 200 using the printed-wiring board 101. In FIG. 14, components which are the same or correspond to those shown in FIG. 11 and FIG. 13 are denoted by the same corresponding reference numerals, respectively, and the description thereof is not given.
A semiconductor chip 113 is attached to the solder resist 104 in the center portion on the top surface of the printed-wiring board 101 by using a paste 112. An Au wire 111, which is a metal thin wire electrically connected to an electrode pad (not shown) on the semiconductor chip 113, is connected to the bonding pad 106 in the bonding pad positioning area 105. Thus, the semiconductor chip 113 is electrically connected to the bonding pad 106. Further, the semiconductor chip 113, the printed-wiring board 101, the paste 112, and the Au wire 111 are collectively sealed in a sealing resin 117.
The number of times the solder resist is applied to the surface of the wiring substrate for use in the semiconductor apparatus is one. There is a problem that, in the process of fabricating a semiconductor apparatus, a contact between the applied solder resist and a solder resist of a bonding tool (capillary) used for connection (wire bonding) of the metal thin wire causes uncleanness and/or deformation of the metal thin wire. In order to solve the problems, in general, the thickness of the solder resist to be applied to the surface of the wiring substrate for use in the semiconductor apparatus is smaller than about 30 μm. Further, as disclosed in Japanese Laid-Open Patent Publication No. 10-294549, in some configuration, the solder resist is thickly applied around the sealing resin in order to reduce a range in which the sealing resin is applied.
However, in the conventional wiring substrate for use in the semiconductor apparatus, unevenness is increased due to the vias and wirings in an area in which the semiconductor chip is mounted, and therefore bubbles (voids) are easily generated between an adhering component and the wiring substrate for use in the semiconductor apparatus, or between an adhering component and the semiconductor chip when the semiconductor chip is mounted. Therefore, in the fabrication process, in the inspection process, in practical use, and the like, when a temperature is increased, there is a problem that a separation between the semiconductor chip and the wiring substrate for use in the semiconductor apparatus may occur.